The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

Mar. 11, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Jing Xie, University Park, PA (US);

Yang Du, Carlsbad, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 23/522 (2006.01); G11C 5/14 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); H01L 23/5226 (2013.01); G06F 17/5068 (2013.01); G11C 5/14 (2013.01); G06F 1/32 (2013.01); G06F 2217/62 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The disclosed embodiments comprise a multi-stage circuit operating across different power domains. The multi-stage circuit may be implemented as a master-slave flip-flop circuit integrated with a level shifter that transfers data across different power domains. The master and slave stages of the flip-flop may be split across two tiers of a 3D IC and may include (i) a level shifter across different power domain integrated within the flip-flop circuit, (ii) reduced one-state writing delays by a self-induced power collapsing technique, (iii) splitting flip-flop power supplies in different tiers using monolithic 3D IC technology, and (iv) cross power domain data transfer between 3D IC tiers.


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