The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

Dec. 20, 2006
Applicants:

Hong Beom Pyeon, Kanata, CA;

Hakjune OH, Kanata, CA;

Jin-ki Kim, Ottawa, CA;

Steven Przybylski, Ann Arbor, MI (US);

Inventors:

Hong Beom Pyeon, Kanata, CA;

HakJune Oh, Kanata, CA;

Jin-Ki Kim, Ottawa, CA;

Steven Przybylski, Ann Arbor, MI (US);

Assignee:

NovaChips Canada Inc., Ottawa, Ontario, CA;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G11C 7/20 (2006.01); G06F 13/42 (2006.01); G11C 7/10 (2006.01); G11C 19/00 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 7/20 (2013.01); G06F 13/4291 (2013.01); G11C 7/10 (2013.01); G11C 7/1003 (2013.01); G11C 19/00 (2013.01); G11C 2029/4402 (2013.01);
Abstract

A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The generated ID is transferred to another device and the ID is incremented in each of the devices in the serial interconnection. The last device in the interconnection provides a last generated ID that is provided to a memory controller having a recognition circuit that recognizes the total number of the serially interconnected devices, from the provided last generated ID. The recognition circuit recognizes the total output latency of the devices in the serial interconnection.


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