The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

May. 19, 2011
Applicants:

Ushasri Merugu, Puppal Guda, IN;

Siva V. N. Hemasunder Tallury, Hyderabad, IN;

Sudheer Kumar Koppolu, Proddatur, IN;

Inventors:

Ushasri Merugu, Puppal Guda, IN;

Siva V. N. Hemasunder Tallury, Hyderabad, IN;

Sudheer Kumar Koppolu, Proddatur, IN;

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/3177 (2006.01); G01R 31/317 (2006.01); G01R 13/34 (2006.01); G01R 13/32 (2006.01); G06F 11/25 (2006.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/28 (2013.01); G01R 31/31701 (2013.01); G01R 13/345 (2013.01); G01R 13/32 (2013.01); G06F 11/25 (2013.01); G06F 11/348 (2013.01);
Abstract

Systems and methods gather data for debugging a circuit-under-test. The system includes a trigger-and-capture circuit, a data compressor, a direct memory access controller, and a memory controller. The trigger-and-capture circuit is coupled to the circuit-under-test for receiving signals from the circuit-under-test. The trigger-and-capture circuit is configured to assert a trigger signal when the signals match a trigger condition. The data compressor is configured to loss-lessly compress the signals into compressed data. The direct memory access controller is configured to generate write and read requests. The write requests write the compressed data to a memory integrated circuit die, and the read requests read the compressed data from the memory integrated circuit die. The memory controller is configured to perform the write and read requests.


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