The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

Mar. 23, 2011
Applicants:

Edoardo Charbon, The Hague, NL;

Mohammad Azim Karami, Delft, NL;

Inventors:

Edoardo Charbon, The Hague, NL;

Mohammad Azim Karami, Delft, NL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/10 (2006.01); G02B 6/122 (2006.01); B82Y 20/00 (2011.01); G02B 5/00 (2006.01);
U.S. Cl.
CPC ...
G02B 6/1226 (2013.01); G02B 5/008 (2013.01); B82Y 20/00 (2013.01);
Abstract

Waveguide structure for propagating a surface plasmon polariton, including an inter-metal plasmonic waveguide (). The waveguide structure has two metal strip like structures () positioned parallel to each other and an isolating material structure () positioned between the two metal strip like structures (). The two metal strip like structures () are positioned at a fixed distance (d) from each other. The inter-metal plasmonic waveguide () is provided in a single layer of a CMOS processed substrate (). Several waveguide structures () may be combined with a crystal like structure () to build logic gates, such as a switch having a gate, source and drain terminal (G,S,D). Using three dimensional designs spanning several layers in a CMOS processed substrate () very complex yet compact logic circuits may be designed.


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