The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

Aug. 31, 2011
Applicants:

Keshav Govind Kamble, Fremont, CA (US);

Alexander Philip Campbell, Kanata, CA;

Atul A. Tambe, Cupertino, CA (US);

Vijoy A. Pandey, San Jose, CA (US);

Inventors:

Keshav Govind Kamble, Fremont, CA (US);

Alexander Philip Campbell, Kanata, CA;

Atul A. Tambe, Cupertino, CA (US);

Vijoy A. Pandey, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/931 (2013.01);
U.S. Cl.
CPC ...
H04L 49/356 (2013.01); H04L 49/40 (2013.01); H04L 49/45 (2013.01);
Abstract

A system includes scaled-out fabric coupler (SFC) boxes and distributed line card (DLC) boxes. Each SFC box has fabric ports and a cell-based switch fabric for switching cells. Each DLC box is in communication with every SFC box. Each DLC box has network ports receiving packets and network processors. Each processor has a fabric interface that provides SerDes channels. The processors divide each packet received over the network ports into cells and distribute the cells of each packet across the SerDes channels. Each DLC box further comprises DLC fabric ports through which the DLC is in communication with the SFCs. Each DLC fabric port includes a pluggable interface with a given number of lanes over which to transmit and receive cells. Each lane is mapped to one of the SerDes channels such that an equal number of SerDes channels of each fabric interface is mapped to each DLC fabric port.


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