Memory interface circuit and timing adjusting method

Abstract

A memory interface circuit, which controls capture timing of data provided from a memory according to a strobe signal provided from the memory, includes a control unit that controls an activation timing of an internal strobe gate signal, which masks the strobe signal when being deactivated, by delaying the internal strobe gate signal by a first period shorter than one cycle time of a clock signal to generate an internal strobe gate adjustment signal, and by adjusting an activation timing of the adjustment signal. A detection unit outputs a detection signal, when the strobe signal changes from a first potential to a second potential higher than the first potential, or when the first potential of the strobe signal continues for a second period or longer. The control unit adjusts the activation timing of the adjustment signal in accordance with the detection signal.