The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

Jul. 03, 2012
Applicants:

Hsiao-hua LU, Chu-Pei, TW;

Chih-ming Kuo, Chu-Pei, TW;

Yu-chun Wang, Chu-Pei, TW;

Inventors:

Hsiao-Hua Lu, Chu-Pei, TW;

Chih-Ming Kuo, Chu-Pei, TW;

Yu-Chun Wang, Chu-Pei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory erasing method and a driving circuit thereof are introduced, when cells are selected to be erased, the method includes setting gates of cells which are not selected to be erased and are located at a selected block, drains of all the cells in a selected bank, and the gate of the unselected cells to be floating; supplying a positive voltage to all the sources in a selected bank and their shared P well and N well; and supplying a negative voltage to the gates of the cells located in a selected block and selected to be erased. Accordingly, a positive coupling voltage from P wells is received whenever gates are floating, so as to inhibit erasure of unselected blocks and thereby streamline decoding, thus making it easy to attain further expansion of blocks or banks with a small layout area and partition of sectors in the blocks.


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