The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

Mar. 15, 2013
Applicant:

Samsung Electro-mechanics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Young Seuck Yoo, Suwon-si, KR;

Kang Heon Hur, Suwon-si, KP;

Jun Hee Bae, Suwon-si, KR;

Yong Suk Kim, Suwon-si, KR;

Sang Moon Lee, Suwon-si, KR;

Won Chul Sim, Suwon-si, KR;

Young Do Kweon, Suwon-si, KR;

Sung Kwon Wi, Suwon-si, KR;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01F 17/00 (2006.01); H01F 5/00 (2006.01); H01F 27/28 (2006.01); H01F 27/24 (2006.01); H01F 27/40 (2006.01);
U.S. Cl.
CPC ...
H01F 27/40 (2013.01); H01F 17/0013 (2013.01); H01F 2017/0026 (2013.01); H01F 2017/0066 (2013.01);
Abstract

Disclosed herein is a common mode filter with an ESD protection pattern built therein. The common mode filter includes a base substrate that is made of an insulating material, a first insulating layer that is formed on the base substrate, a coil-shaped internal electrode that is formed on the first insulating layer, a second insulating layer that is formed on the internal electrode, a first external electrode terminal that is formed on the second insulating layer, a first ferrite resin layer that is formed on the second insulating layer and receives the first external electrode terminal, an ESD protection pattern that is formed on the first external electrode terminal, a second external electrode terminal that is formed on the ESD protection pattern, and a second ferrite resin layer that is formed on the first ferrite resin layer and receives the second external electrode terminal.


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