The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2015
Filed:
Nov. 29, 2012
Agate Logic Inc., Sunnyvale, CA (US);
Kai Keung Chan, Fremont, CA (US);
David Tsang, Los Altos, CA (US);
Shian-Jiun Fu, Sunnyvale, CA (US);
Chao-Chiang Chen, Cupertino, CA (US);
Agate Logic, Inc., Santa Clara, CA (US);
Abstract
A logic processing device, containing an application specific integrated circuit ('ASIC') and field programmable gate array ('FPGA'), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.