The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

Mar. 23, 2012
Applicants:

Christian Lavoie, Ossining, NY (US);

Dong-ick Lee, Fishkill, NY (US);

Ahmet Serkan Ozcan, Pleasantville, NY (US);

Zhen Zhang, Ossining, NY (US);

Inventors:

Christian Lavoie, Ossining, NY (US);

Dong-Ick Lee, Fishkill, NY (US);

Ahmet Serkan Ozcan, Pleasantville, NY (US);

Zhen Zhang, Ossining, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 21/285 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28518 (2013.01); H01L 29/665 (2013.01);
Abstract

In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.


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