The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

May. 09, 2012
Applicants:

Sehat Sutardja, Los Altos Hills, CA (US);

Ravishanker Krishnamoorthy, Singapore, SG;

Siew Yong Chui, Singapore, SG;

Inventors:

Sehat Sutardja, Los Altos Hills, CA (US);

Ravishanker Krishnamoorthy, Singapore, SG;

Siew Yong Chui, Singapore, SG;

Assignee:

Marvell World Trade Ltd., St. Michael, BB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7817 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/7835 (2013.01); H01L 29/0847 (2013.01); H01L 29/0878 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET).


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