Power semiconductor field effect transistor structure with charge trapping material in the gate dielectric

Abstract

The subject disclosure presents power semiconductor devices, and methods for manufacture thereof, with improved ruggedness and. In an aspect, the power semiconductor devices are power field effect transistors (FETs) having enhanced suppression of the activation of the parasitic bipolar junction transistor (BJT) and a normal threshold value. The devices comprise a doped source () of a first conductivity type, a doped body () of a second conductivity type, a source electrode () short-connecting the doped body and the doped source, a doped drift region () of the first conductivity type, a first layer () of a gate dielectric region () covering the surface of the doped drift region (), and forming channel from the doped source () to the doped drift region (), a second layer () of the gate dielectric region () over the first layer (), a third layer () of the gate dielectric region () over the second layer (), and a gate electrode () over the third layer ().