The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

Sep. 20, 2013
Applicant:

Sandisk Corporation, Milpitas, CA (US);

Inventors:

Jian Chen, Sunnyvale, CA (US);

Xiangfeng Duan, Los Angeles, CA (US);

Chao Liu, San Jose, CA (US);

Madhuri Nallabolu, Sunnyvale, CA (US);

J. Wallace Parce, Palo Alto, CA (US);

Srikanth Ranganathan, Mountain View, CA (US);

Assignee:

SanDisk Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/66 (2006.01); G03F 7/075 (2006.01); G03F 7/16 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); B82Y 10/00 (2011.01); B82Y 30/00 (2011.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66477 (2013.01); B82Y 10/00 (2013.01); B82Y 30/00 (2013.01); G03F 7/0754 (2013.01); G03F 7/165 (2013.01); G03F 7/168 (2013.01); H01L 21/28273 (2013.01); H01L 21/823437 (2013.01); H01L 21/823828 (2013.01); H01L 29/42332 (2013.01); H01L 29/78 (2013.01);
Abstract

Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing also are provided.


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