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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8981436 B1

PDFFull Text
Date of Patent:
Mar. 17, 2015

Filed:

Sep. 30, 2013

Stacked structure, spin transistor, and reconfigurable logic circuit

Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Yoshiaki Saito, Kawasaki, JP;

Tomoaki Inokuchi, Yokohama, JP;

Mizue Ishikawa, Yokohama, JP;

Hideyuki Sugiyama, Kawasaki, JP;

Tetsufumi Tanamoto, Kawasaki, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Evan Pert

Assistant Examiner:

Gustavo Ramallo

Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/108 (2006.01); H01L 29/94 (2006.01); H01L 29/82 (2006.01); H01L 21/00 (2006.01); H01L 43/10 (2006.01); H01L 29/66 (2006.01); H03K 19/173 (2006.01); H03K 19/18 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
H01L 43/10 (2013.01); H01L 29/66984 (2013.01); H03K 19/1733 (2013.01); H03K 19/18 (2013.01); H03K 19/17728 (2013.01);
Abstract

A stacked structure according to an embodiment includes: a semiconductor layer; a first layer formed on the semiconductor layer, the first layer containing at least one element selected from Zr, Ti, and Hf, the first layer being not thinner than a monoatomic layer and not thicker than a pentatomic layer; a tunnel barrier layer formed on the first layer; and a magnetic layer formed on the tunnel barrier layer.

Find Patent Forward Citations

Saito, Yoshiaki. (2015). Stacked structure, spin transistor, and reconfigurable logic circuit (U.S. Patent No. 8981436). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8981436

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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