The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

May. 17, 2012
Applicants:

Moon-gi Cho, Suwon-Si, KR;

Sang-hee Lee, Yongin-si, KR;

Jeong-woo Park, Suwon-si, KR;

Inventors:

Moon-gi Cho, Suwon-Si, KR;

Sang-hee Lee, Yongin-si, KR;

Jeong-woo Park, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/13 (2013.01); H01L 24/11 (2013.01); H01L 2224/03 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/1147 (2013.01); H01L 2224/1181 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/11902 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/03912 (2013.01);
Abstract

A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose the seed layer on the pads; forming pillars by performing a primary electroplating on a region exposed by the photoresist pattern; forming a solder layer by performing a secondary electroplating on the pillars; removing the photoresist pattern; forming solder bumps, in which solders partially cover surfaces of the pillars, by performing a reflow process on the semiconductor substrate; and removing portions of the seed layer formed in regions other than the solder bumps.


Find Patent Forward Citations

Cho, Moon-gi. (2015). Solder collapse free bumping process of semiconductor device (U.S. Patent No. 8980739). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8980739

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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