The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2015
Filed:
Feb. 13, 2013
Applicant:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Inventors:
Hiroshi Yamada, Kanagawa, JP;
Yutaka Onozuka, Kanagawa, JP;
Atsuko Iida, Kanagawa, JP;
Kazuhiko Itaya, Kanagawa, JP;
Assignee:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/02 (2006.01); H01L 21/78 (2006.01); H01L 23/495 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 23/495 (2013.01); H01L 21/56 (2013.01); H01L 23/3135 (2013.01); H01L 23/49572 (2013.01); H01L 21/563 (2013.01); H01L 24/24 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/49171 (2013.01); H01L 2224/97 (2013.01);
Abstract
A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip.