The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2015

Filed:

Mar. 25, 2010
Applicants:

Evgeny N. Veselov, Sammamish, WA (US);

Rossen Petkov Atanassov, Bellevue, WA (US);

Michael Jacob Jolson, Seattle, WA (US);

Inventors:

Evgeny N. Veselov, Sammamish, WA (US);

Rossen Petkov Atanassov, Bellevue, WA (US);

Michael Jacob Jolson, Seattle, WA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 17/21 (2006.01);
U.S. Cl.
CPC ...
G06F 17/211 (2013.01);
Abstract

Layout processing techniques have been described that allow processing of structured documents to be conducted, and for associated layout to be accomplished in a sequential manner. The layout process is split into multiple, smaller steps that can be executed sequentially. In at least some embodiments, a layout builder is utilized in conjunction with a stack to control layout execution on respective levels of the structural hierarchy of a structured document. Immutable data structures are utilized and allow for parallel execution of sequential layout operations. In at least some embodiments, partial execution of the layout sequence can be performed to produce usable data.


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