The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2015

Filed:

Feb. 05, 2007
Applicant:

Russell H. Fish, Iii, Dallas, TX (US);

Inventor:

Russell H. Fish, III, Dallas, TX (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2006.01); G06F 9/30 (2006.01); G06F 9/32 (2006.01); G06F 12/08 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3851 (2013.01); G06F 9/30138 (2013.01); G06F 9/30145 (2013.01); G06F 9/322 (2013.01); G06F 9/38 (2013.01); G06F 9/3867 (2013.01); G06F 9/3885 (2013.01); G06F 9/3891 (2013.01); G06F 12/0875 (2013.01); G06F 15/7846 (2013.01);
Abstract

In one aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors; wherein each of the processors is operable to process a de minimis instruction set, and wherein each of the processors comprises local caches dedicated to each of at least three specific registers in the processor. In another aspect, the invention comprises a system comprising: (a) a plurality of parallel processors on a single chip; and (b) computer memory located on the chip and accessible by each of the processors, wherein each of the processors is operable to process an instruction set optimized for thread-level parallel processing.


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