The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2015

Filed:

Dec. 21, 2007
Applicants:

Antony John Penton, Cambridge, GB;

Alex James Waugh, Cambridge, GB;

Andrew Christopher Rose, Cambridge, GB;

Paul Stanley Hughes, Sunnyvale, CA (US);

Inventors:

Antony John Penton, Cambridge, GB;

Alex James Waugh, Cambridge, GB;

Andrew Christopher Rose, Cambridge, GB;

Paul Stanley Hughes, Sunnyvale, CA (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/08 (2006.01); G06F 11/10 (2006.01); G11C 29/42 (2006.01); G11C 29/00 (2006.01); G11C 15/00 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0864 (2013.01); G06F 11/1064 (2013.01); G11C 29/42 (2013.01); G11C 29/76 (2013.01); G11C 15/00 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01);
Abstract

A data processing apparatus and method are provided for handling hard errors occurring in a cache of the data processing apparatus. Cache location avoid storage is provided having at least one record, with each record being used to store a cache line identifier identifying a specific cache line. On detection of an error condition, one of the records in the cache location avoid storage is allocated to store the cache line identifier for the specific cache line associated with the entry for which the error condition was detected. A clean and invalidate operation is performed in respect of the specific cache line, and the access request is then re-performed. Cache access circuitry is arranged to exclude any specific cache line identified in the cache location avoid storage from a lookup procedure.


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