The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2015

Filed:

Feb. 25, 2014
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Kieron Turkington, London, GB;

Vivek Gowri-Shankar, Oxford, GB;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/00 (2011.01); H04N 5/21 (2006.01); G06T 5/00 (2006.01); G06T 5/50 (2006.01); H04N 5/213 (2006.01);
U.S. Cl.
CPC ...
H04N 5/21 (2013.01); G06T 5/002 (2013.01); G06T 5/50 (2013.01); G06T 2207/10016 (2013.01); H04N 5/213 (2013.01);
Abstract

Various embodiments of the present disclosure provide techniques for performing video denoising (VDN). An adaptive noise threshold is dynamically determined and used to distinguish between frame to frame differences in pixel values that relate to image motion from those differences that relate to noise. The disclosed techniques enable the noise threshold to be continuously updated, for example as frequently as once per frame, so that the noise threshold may closely track to varying levels of noise in the input video data. The techniques may be implemented in, for example, a video format conversion apparatus. Advantageously, the techniques may be incorporated in programmable logic devices (PLD's) or Field Programmable Gate Arrays (FPGA's) configurable to perform video format conversion, while adding only modest additional computational demands on the apparatus.


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