The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2015
Filed:
Oct. 04, 2013
Amlogic Co., Ltd., Santa Clara, CA (US);
Weicheng Zhang, Shanghai, CN;
Ming Shi, Shanghai, CN;
Wei-Hua Zou, Shanghai, CN;
Shu-Sun Yu, Cupertino, CA (US);
Chieh-Yuan Chao, Fremont, CA (US);
Amlogic Co., Ltd., Santa Clara, CA (US);
Abstract
Some embodiments of the present invention provide a method and apparatus for a Vernier ring time to digital converter having a single clock input and an all digital circuit that calculates a fixed delay relationship between a set of slow buffers and fast buffers. A method for calibrating a Vernier Delay Line of a TDC, comprising the steps of inputting a reference clock to a slow buffer and to a fast buffer, determining a delay ratio of the slow buffer and fast buffer; and adjusting the delay ratio of the slow buffer and fast buffer to a fixed delay ratio value wherein an up-down accumulator generates control signals to adjust the slow buffer.