The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2015
Filed:
Nov. 13, 2012
Applicant:
Honeywell International Inc., Morristown, NJ (US);
Inventors:
Paul S. Fechner, Plymouth, MN (US);
Weston Roper, Shakopee, MN (US);
James D. Seefeldt, Eden Prairie, MN (US);
Assignee:
Honeywell International Inc., Morristown, NJ (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/01 (2006.01); H03K 19/094 (2006.01);
U.S. Cl.
CPC ...
H03K 19/09421 (2013.01); H03K 3/01 (2013.01);
Abstract
This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.