The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2015

Filed:

Feb. 26, 2014
Applicants:

Wenzhong Zhang, Tianjin, CN;

Chris C. Dao, Pflugerville, TX (US);

Jehoda Refaeli, Austin, TX (US);

Yi Zhao, Tianjin, CN;

Inventors:

Wenzhong Zhang, Tianjin, CN;

Chris C. Dao, Pflugerville, TX (US);

Jehoda Refaeli, Austin, TX (US);

Yi Zhao, Tianjin, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/22 (2006.01); H03K 3/3565 (2006.01);
U.S. Cl.
CPC ...
H03K 3/3565 (2013.01);
Abstract

A comparator used in a clock signal generation circuit compares two input signals and generates an output signal. The comparator has first and second input transistors coupled to the input signals. First and second hysteresis transistors are coupled between the input transistors and an output stage of the comparator, and apply hysteresis to a comparison of the input signals. First and second hysteresis control transistors are coupled between the input transistors and the hysteresis transistors to isolate the hysteresis transistors from the input transistors under control of a hysteresis enable signal. The comparator is operable in a first mode or a second mode based on a hysteresis enable signal. In the first mode the comparator applies hysteresis to the comparison of the input signals and in the second mode, compares the input signals without hysteresis.


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