The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2015

Filed:

Aug. 30, 2012
Applicants:

Toshiki Furutani, Ogaki, JP;

Takeshi Furusawa, Ogaki, JP;

Inventors:

Toshiki Furutani, Ogaki, JP;

Takeshi Furusawa, Ogaki, JP;

Assignee:

IBIDEN Co., Ltd., Ogaki-shi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 23/053 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49541 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/3511 (2013.01); H01L 23/49827 (2013.01);
Abstract

A printed wiring board includes a substrate, a first buildup formed on a first surface of the substrate and including the outermost conductive layer, and a second buildup layer formed on a second surface of the substrate and including the outermost conductive layer. The outermost layer of the first buildup has pads positioned to connect a semiconductor component, the first buildup has a component mounting region directly under the component such that the outermost layer of the first buildup has a portion in the region, the outermost layer of the second buildup has a portion directly under the region, and the portions satisfy the ratio in the range of from 1.1 to 1.35, where the ratio is obtained by dividing a planar area of the portion of the second buildup by a planar area of the portion of the first buildup.


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