The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2015

Filed:

Dec. 01, 2009
Applicants:

Yasuhiro Hamada, Tokyo, JP;

Shuya Kishimoto, Tokyo, JP;

Kenichi Maruhashi, Tokyo, JP;

Inventors:

Yasuhiro Hamada, Tokyo, JP;

Shuya Kishimoto, Tokyo, JP;

Kenichi Maruhashi, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 23/522 (2006.01); H01L 23/66 (2006.01); H03F 1/30 (2006.01); H03F 3/195 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5227 (2013.01); H01L 23/5225 (2013.01); H01L 23/66 (2013.01); H03F 1/301 (2013.01); H03F 3/195 (2013.01); H01L 27/0676 (2013.01); H01L 2223/6644 (2013.01); H01L 2223/665 (2013.01); H01L 2223/6655 (2013.01); H01L 2924/3011 (2013.01); H03F 2200/18 (2013.01); H03F 2200/222 (2013.01); H03F 2200/255 (2013.01); H03F 2200/387 (2013.01); H03F 2200/423 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A bias circuit according to the present invention includes a resistor layerwhich is placed above a substrateand connected to a ground potential, and a conductorfor forming an inductorplaced above the resistor layer. Further, a manufacturing method of the bias circuit according to the present invention generates the resistor layerabove the substrateand is connected to the ground potential, and generates the conductorfor forming the inductorabove the resistor layer. The present invention can provide a bias circuit and a manufacturing method of the bias circuit that enables easy integration on a semiconductor substrate and prevents parasitic oscillation.


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