Single-poly non-volatile memory cell

Abstract

A single-poly NVM cell includes a substrate having an isolation region separating a first OD region from a second OD region, a read transistor within the first OD region, and a coupling capacitor within the second OD region. A first ion well completely overlaps with the first oxide define region. The read transistor includes a drain region, a source region, a channel region, a single-poly floating gate overlying the channel region, and a gate dielectric layer between the floating gate and the channel region. The coupling capacitor includes a shallow ion well, a heavily-doped, ultra-shallow dopant region in the shallow ion well, a single-poly charge-storage floating gate overlying the heavily-doped, ultra-shallow dopant region, and a gate dielectric layer under the charge storage floating gate. The shallow ion well has a junction depth that is substantially equal to or shallower than a trench depth of the isolation region.