The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2015

Filed:

Jun. 15, 2011
Applicants:

Hye-rim Han, Seongnam-si, KR;

Byoung-sun NA, Hwaseong-si, KR;

Jae-jin Song, Hwaseong-si, KR;

Hyung-jun Park, Seongnam-si, KR;

SI Hyun Ahn, Cheonan-si, KR;

Woo-jung Shin, Ansan-si, KR;

Inventors:

Hye-Rim Han, Seongnam-si, KR;

Byoung-Sun Na, Hwaseong-si, KR;

Jae-Jin Song, Hwaseong-si, KR;

Hyung-Jun Park, Seongnam-si, KR;

Si Hyun Ahn, Cheonan-si, KR;

Woo-Jung Shin, Ansan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 27/12 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); H01L 27/0288 (2013.01);
Abstract

The present invention relates to a thin film transistor array panel including: a substrate; gate lines formed on the substrate; and a gate driver formed on the substrate to apply gate signals to the gate lines. The gate driver includes a first wire and a second wire to transmit different signals, and at least one of the first wire and the second wire includes a static electricity preventing structure to prevent static electricity from accumulating between the first wire and the second wire.


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