The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2015
Filed:
Nov. 26, 2012
Applicant:
Fujitsu Limited, Kanagawa, JP;
Inventors:
Chihiro Uchibori, Campbell, CA (US);
Michael G. Lee, Saratoga, CA (US);
Assignee:
Fujitsu Limited, Kawasaki-shi, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 22/10 (2013.01); H01L 23/48 (2013.01); H01L 2224/16225 (2013.01); H01L 24/16 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/3511 (2013.01); H01L 23/562 (2013.01);
Abstract
A semiconductor assembly includes a first substrate and a chip. The chip is coupled to and spaced apart from the substrate. Further, the chip has a first surface facing the substrate. The chip also has a warpage profile indicating stress imparted on the chip following a reflow operation. The assembly includes a back layer disposed on the chip on a second surface substantially opposite from the first surface. The back layer has a non-uniform thickness. Additionally, the thickness of the back layer on each of a plurality of elements of the chip is based on the warpage profile.