The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2015

Filed:

Feb. 11, 2009
Applicant:

Thomas Keyser, Plymouth, MN (US);

Inventor:

Thomas Keyser, Plymouth, MN (US);

Assignee:

Honeywell International Inc., Morristown, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 9/00 (2006.01); H05K 3/00 (2006.01); H01R 43/00 (2006.01); H01L 23/532 (2006.01); B81C 1/00 (2006.01); H01C 17/06 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 27/08 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53276 (2013.01); B81C 1/00095 (2013.01); H01C 17/06 (2013.01); H01L 21/76838 (2013.01); H01L 23/5228 (2013.01); H01L 27/0802 (2013.01); H01L 2221/1094 (2013.01);
Abstract

A method of forming nanotube contact structures may include forming an interconnect layer over a portion of a layer of a microelectronics device and forming a nanotube layer over a portion of the interconnect layer. The nanotube layer may define openings through the nanotube layer. The method also may include forming self-aligned electrodes in the openings of the nanotube layer such that the self-aligned electrodes are formed only in openings in the nanotube layer that substantially reside over metal filled vias of the microelectronics device. In some examples, the self-aligned electrodes may be formed on the metal in the vias, and the self-aligned electrodes may not be formed in openings that do not reside over the metal filled vias.


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