The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2015

Filed:

May. 14, 2012
Applicants:

Rajesh Mittal, Bangalore, IN;

Puneet Sabbarwal, Agra, IN;

Prakash Narayanan, Bangalore, IN;

Rubin Ajit Parekhji, Bangalore, IN;

Inventors:

Rajesh Mittal, Bangalore, IN;

Puneet Sabbarwal, Agra, IN;

Prakash Narayanan, Bangalore, IN;

Rubin Ajit Parekhji, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/3185 (2006.01); G01R 31/3183 (2006.01); G01R 31/3177 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318555 (2013.01); G01R 31/3183 (2013.01); G01R 31/318533 (2013.01); G01R 31/318544 (2013.01); G01R 31/318536 (2013.01); G01R 31/318569 (2013.01); G01R 31/318594 (2013.01); G01R 31/3177 (2013.01);
Abstract

Various embodiments of methods and integrated circuits capable of generating a test mode control signal for a scan test through a scan chain (such as in an integrated circuit) are provided. The integrated circuit includes a test pattern detection block, a counter circuit, and a control circuit. The test pattern detection block is configured to receive a detection pattern and to detect a first pattern corresponding to a shift phase and a second pattern corresponding to a capture phase of a test pattern based on the detection pattern and to generate a trigger signal based upon the detection of the patterns. The control circuit generates and controls the test mode control signal based on the count states. The counter circuit is configured to generate one or more count states corresponding to one of the shift phase, the capture phase and the clock signal based on the detected pattern.


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