The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2015

Filed:

Feb. 19, 2014
Applicant:

Lsi Corporation, San Jose, CA (US);

Inventors:

Peter Kiss, Basking Ridge, NJ (US);

Said E. Abdelli, Minneapolis, MN (US);

Donald R. Laturell, Oak Hill, FL (US);

Ross S. Wilson, Menlo Park, CA (US);

James F. MacDonald, Stillwater, MN (US);

Assignee:

LSI Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 9/00 (2006.01); H04L 25/02 (2006.01); H03M 3/00 (2006.01); H03F 3/217 (2006.01); H03H 17/00 (2006.01); H03H 17/02 (2006.01); H04L 27/02 (2006.01);
U.S. Cl.
CPC ...
H03M 9/00 (2013.01); H04L 25/02 (2013.01); H03M 3/30 (2013.01); H03F 3/217 (2013.01); H03H 17/0018 (2013.01); H03H 17/0273 (2013.01); H03H 17/028 (2013.01); H04L 27/02 (2013.01); H03F 2200/331 (2013.01);
Abstract

In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.


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