The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2015
Filed:
Apr. 22, 2008
Applicant:
Guo Jun Ren, San Jose, CA (US);
Inventor:
Guo Jun Ren, San Jose, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03H 11/26 (2006.01); H01L 35/00 (2006.01); H01L 37/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
An integrated circuit that equalizes delay across process corners. A delay equalizer circuit is used to adjust and maintain a relatively constant delay across different process corners. The delay equalizer circuit includes a process monitor and a delay compensator circuit coupled to the process monitor. The process monitor may output a compensating bias voltage for a pMOS transistor and a compensating bias voltage for an nMOS transistor. The compensating bias voltages may be used to regulate and maintain a relatively constant delay through the delay compensator circuit across varying process corners.