The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2015

Filed:

Feb. 22, 2013
Applicant:

The Board of Trustees of the Leland Stanford Junior University, Palo Alto, CA (US);

Inventors:

Ashish Pal, Stanford, CA (US);

Aneesh Nainani, Palo Alto, CA (US);

Krishna Chandra Saraswat, Saratoga, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/108 (2006.01); H01L 29/778 (2006.01); H01L 29/786 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/267 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7831 (2013.01); H01L 29/66477 (2013.01); H01L 29/66484 (2013.01); H01L 21/845 (2013.01); H01L 29/7841 (2013.01); H01L 27/10802 (2013.01); H01L 27/1211 (2013.01); H01L 29/267 (2013.01); H01L 29/7782 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01);
Abstract

Various aspects of the invention are directed to memory circuits and their implementation. According to an example embodiment, an apparatus includes a channel region between raised source and drain regions which are configured and arranged with respective bandgap offsets relative to the channel region to confine carriers in the channel region. The apparatus also includes front and back gates respectively separated from the channel region by gate dielectrics. The raised source and drain regions have respective portions laterally adjacent the front gate and adjacent the channel region. Carriers are stored in the channel region via application of voltage(s) to the front and back gates, and relative to bias(es) at the source and drain regions.


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