The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2015

Filed:

Aug. 02, 2012
Applicants:

Gregg A. Bouchard, Georgetown, TX (US);

Rajan Goyal, Saratoga, CA (US);

Jeffrey A. Pangborn, Saratoga, CA (US);

Najeeb I. Ansari, San Jose, CA (US);

Inventors:

Gregg A. Bouchard, Georgetown, TX (US);

Rajan Goyal, Saratoga, CA (US);

Jeffrey A. Pangborn, Saratoga, CA (US);

Najeeb I. Ansari, San Jose, CA (US);

Assignee:

Cavium, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 9/46 (2006.01); G06F 13/16 (2006.01); G06F 12/08 (2006.01); G06F 12/02 (2006.01); G06F 12/04 (2006.01); G06N 5/02 (2006.01); H04L 12/26 (2006.01); H04L 29/06 (2006.01); H04L 12/747 (2013.01); H04L 12/851 (2013.01); H04L 12/801 (2013.01); H04L 12/741 (2013.01); G06F 9/50 (2006.01); H04L 29/08 (2006.01);
U.S. Cl.
CPC ...
G06F 9/46 (2013.01); G06F 13/16 (2013.01); G06F 12/0802 (2013.01); G06F 12/0207 (2013.01); G06F 12/04 (2013.01); G06N 5/02 (2013.01); H04L 43/18 (2013.01); H04L 63/0227 (2013.01); H04L 45/742 (2013.01); H04L 47/2441 (2013.01); H04L 47/39 (2013.01); H04L 69/22 (2013.01); H04L 45/745 (2013.01); G06F 9/5027 (2013.01); H04L 67/10 (2013.01);
Abstract

According to an example embodiment, a processor is provided including an integrated on-chip memory device component. The on-chip memory device component includes a plurality of memory banks, and multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, enabling access to multiple memory banks, among the plurality of memory banks, per clock cycle, each memory bank accessible by a single logical port per clock cycle and each logical port accessing a single memory bank per clock cycle.


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