The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2015

Filed:

May. 14, 2012
Applicants:

Hye-jin Kim, Seoul, KR;

Kwang-jin Lee, Hwaseong-si, KR;

Du-eung Kim, Yongin-si, KR;

Hung-jun an, Hwaseong-si, KR;

Inventors:

Hye-Jin Kim, Seoul, KR;

Kwang-Jin Lee, Hwaseong-si, KR;

Du-Eung Kim, Yongin-si, KR;

Hung-Jun An, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 7/10 (2006.01); G11C 11/22 (2006.01); G11C 13/00 (2006.01); G11C 8/10 (2006.01);
U.S. Cl.
CPC ...
G11C 5/14 (2013.01); G11C 7/1078 (2013.01); G11C 7/1096 (2013.01); G11C 11/22 (2013.01); G11C 13/00 (2013.01); G11C 13/0004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0023 (2013.01); G11C 13/0038 (2013.01); G11C 13/0069 (2013.01); G11C 8/10 (2013.01); G11C 2013/0088 (2013.01); G11C 2013/009 (2013.01); G11C 2213/72 (2013.01);
Abstract

A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator configured to generate a first voltage, a voltage pad configured to receive an external voltage that has a level higher than the first voltage, a write driver configured to be supplied with the external voltage and configured to write data to the plurality of non-volatile memory cells selected from the memory cell array; a sense amplifier configured to be supplied with the external voltage and configured to read data from the plurality of non-volatile memory cells selected from the memory cell array, and a row decoder and a column decoder configured to select the plurality of non-volatile memory cells included in the memory cell array, the row decoder being supplied with the first voltage and the column decoder being supplied with the external voltage.


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