The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2015

Filed:

Sep. 28, 2012
Applicant:

Ps4 Luxco S.a.r.l., Luxembourg, LU;

Inventors:

Kazuhiko Kajigaya, Tokyo, JP;

Kazuo Ono, Tokyo, JP;

Tomonori Sekiguchi, Tokyo, JP;

Assignee:

PS4 Luxco S.a.r.l., Luxembourg, LU;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); H01L 23/498 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01); G11C 5/04 (2006.01); G11C 5/14 (2006.01); H01L 25/065 (2006.01); G11C 7/02 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/498 (2013.01); G11C 5/025 (2013.01); G11C 5/063 (2013.01); G11C 7/1006 (2013.01); G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); G11C 5/02 (2013.01); G11C 5/04 (2013.01); G11C 5/14 (2013.01); G11C 7/1012 (2013.01); H01L 25/0657 (2013.01); G11C 7/02 (2013.01); H01L 25/18 (2013.01); G11C 2207/107 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device is disclosed in which a plurality of memory cores are provided on a semiconductor chip. Each of the memory cores comprises: first and second circuit regions and a first and second through electrode groups. a first power supply is supplied in the first circuit region in which a data bus for parallel data is driven, and a second power supply separated from the first power supply is supplied in the second circuit region in which the parallel data and serial data are bidirectionally converted. The first through electrode group includes through electrodes supplying the first power supply to the first circuit region, and the second through electrode group includes through electrodes supplying the second power supply to the second circuit region.


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