The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2015

Filed:

Feb. 28, 2012
Applicants:

Ankit Srivastava, San Diego, CA (US);

Matthew D. Sienko, San Diego, CA (US);

Meysam Azin, San Diego, CA (US);

Xiaohong Quan, San Diego, CA (US);

Peter J. Shah, San Diego, CA (US);

Inventors:

Ankit Srivastava, San Diego, CA (US);

Matthew D. Sienko, San Diego, CA (US);

Meysam Azin, San Diego, CA (US);

Xiaohong Quan, San Diego, CA (US);

Peter J. Shah, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 3/04 (2006.01); H03F 3/217 (2006.01); H03F 1/04 (2006.01); H03F 99/00 (2009.01); H03G 3/20 (2006.01); H03G 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Techniques for sensing current delivered to a load by a differential output stage, e.g., in a Class D amplifier. In one aspect, voltages across sense resistors coupled in series with first and second branches of the differential output stage are low-passed filtered and digitized. The sense resistors may be coupled in series with the sources of transistors of the first and second branches, wherein the transistors are selectively switchable on and off by input voltage driving voltages. The input driving voltages may correspond to a ternary voltage waveform such that during a given phase, the two transistors coupled in series with the sense resistors may be turned off. Further aspects provide for the first and second branches having cascoded NMOS and/or PMOS transistors, and the sense resistors being provided between a pair of cascoded transistors.


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