The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2015
Filed:
Jul. 19, 2013
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventor:
Steven H. Voldman, South Burlington, VT (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/823892 (2013.01); H01L 27/0921 (2013.01); H01L 29/1079 (2013.01); H01L 29/1083 (2013.01); H01L 29/7816 (2013.01); H01L 29/7835 (2013.01); H01L 29/0638 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/086 (2013.01); H01L 29/0878 (2013.01); H01L 29/1045 (2013.01);
Abstract
Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.
Voldman, Steven. (2015). Structure, structure and method of latch-up immunity for high and low voltage integrated circuits (U.S. Patent No. 8963158). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8963158
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile