The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2015

Filed:

Dec. 11, 2007
Applicants:

Jan-willem Van DE Waerdt, San Jose, CA (US);

Steven Roos, Eindhoven, NL;

Inventors:

Jan-Willem Van De Waerdt, San Jose, CA (US);

Steven Roos, Eindhoven, NL;

Assignee:

Nytell Software LLC, Wilmington, DE (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 8/45 (2013.01); G06F 9/30061 (2013.01); G06F 8/443 (2013.01); G06F 9/3842 (2013.01);
Abstract

Different numbers of delay slots are assigned by a compiler/scheduler to each different type of jump operation in a pipelined processor system. The number of delay slots is variable and kept to the minimum needed by each type of jump operation. A compatible processor uses a corresponding number of branch delay slots to exploit the difference in predictability of different types of branch or jump operations. Different types of jump operations resolved their target addresses in different numbers of delay slots. As a result, the compiler/scheduler is able to generate more efficient code than for a processor with a fixed number of delay slots for all jump types, resulting in better processor performance.


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