The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2015

Filed:

Dec. 12, 2008
Applicants:

Christopher A. Vick, San Jose, CA (US);

Gregory M. Wright, Mountain View, CA (US);

Mark S. Moir, Windham, NH (US);

Inventors:

Christopher A. Vick, San Jose, CA (US);

Gregory M. Wright, Mountain View, CA (US);

Mark S. Moir, Windham, NH (US);

Assignee:

Oracle America, Inc., Redwood Shores, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 9/45 (2006.01); G06F 9/38 (2006.01); G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
G06F 8/52 (2013.01); G06F 9/3834 (2013.01); G06F 9/384 (2013.01); G06F 9/3863 (2013.01); G06F 9/30087 (2013.01); G06F 9/3857 (2013.01); G06F 9/3004 (2013.01);
Abstract

One embodiment of the present invention provides a system that facilitates precise exception semantics for a virtual machine. During operation, the system executes a program in the virtual machine using a processor that includes a gated store buffer that stores values to be written to a memory. This gated store buffer is configured to delay a store to the memory until after a speculatively-optimized region of the program commits. The processor signals an exception when it detects that a load following the store is attempting to access the same memory region being written by the store prior to the commitment of the speculatively-optimized region.


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