The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2015

Filed:

Jan. 07, 2011
Applicant:

Jae Man Yoon, Gyeonggi-Do, KR;

Inventor:

Jae Man Yoon, Gyeonggi-Do, KR;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/02 (2006.01); G11C 7/06 (2006.01); G11C 5/06 (2006.01); G11C 5/02 (2006.01); G11C 11/4094 (2006.01); G11C 11/4097 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G11C 7/06 (2013.01); G11C 5/063 (2013.01); G11C 5/025 (2013.01); G11C 11/4094 (2013.01); G11C 11/4097 (2013.01); G11C 11/4074 (2013.01);
Abstract

A semiconductor memory device including a memory cell array including at least one word line, at least one cell bit line, and at least one memory cell that is disposed in a region where the at least one word line and the at least one cell bit line cross each other; at least one sense amplifier that is disposed above or below the memory cell array to be overlapped with the memory cell array in a planar fashion, connected to at least one bit line connected to the at least one cell bit line, and at least one complementary bit line corresponding to the at least one bit line, and senses data stored in the at least one memory cell; a decompression unit for decompressing a signal having a lower voltage level from among a signal of the at least one bit line and a signal of the at least one complementary bit line; a boosting unit for boosting a signal having a higher voltage level from among the signal of the at least one bit line and the signal of the at least one complementary bit line; and an equalizing unit for equalizing the signal of the at least one bit line and the signal of the at least one complementary bit line.


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