The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2015

Filed:

Aug. 30, 2013
Applicants:

Stichting Imec Nederland, Eindhoven, NL;

Katholieke Universiteit Leuven, Leuven, BE;

Inventors:

Vibhu Sharma, Eindhoven, NL;

Stefan Cosemans, Mol, BE;

Wim Dehaene, Kessel-Lo, BE;

Francky Catthoor, Temse, BE;

Maryam Ashouei, Eindhoven, NL;

Jos Huisken, Waalre, NL;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 11/412 (2006.01); G11C 7/18 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 11/412 (2013.01); G11C 7/18 (2013.01);
Abstract

A memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines.


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