The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2015

Filed:

Sep. 17, 2012
Applicant:

Fairchild Semiconductor Corporation, San Jose, CA (US);

Inventors:

Bin Zhao, Irvine, CA (US);

Victor Lee, Irvine, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/56 (2006.01); G05F 1/46 (2006.01);
U.S. Cl.
CPC ...
G05F 1/46 (2013.01);
Abstract

Generally, this disclosure provides methods and systems for improved startup for DC-DC converters that reduce input voltage droop, in-rush current and output voltage jumps. The system may include a power stage circuitry including a plurality of power segments coupled in parallel, the power stage circuitry is coupled between an input voltage and output stage circuitry and configured to deliver power to a load coupled to the output stage circuitry. The system may further include PWM and power stage controller circuitry configured to sequentially and progressively activate the plurality of power segments to limit an input in-rush current from the input voltage during a ramp up period and output voltage at the output stage circuitry.


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