The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2015

Filed:

Jul. 12, 2013
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Yoshiaki Sugizaki, Kanagawa-ken, JP;

Akihiro Kojima, Kanagawa-ken, JP;

Yosuke Akimoto, Kanagawa-ken, JP;

Hidefumi Yasuda, Kanagawa-ken, JP;

Nozomu Takahashi, Kanagawa-ken, JP;

Kazuhito Higuchi, Kanagawa-ken, JP;

Susumu Obata, Kanagawa-ken, JP;

Hideo Tamura, Kanagawa-ken, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/36 (2010.01); H01L 21/28 (2006.01); H01L 33/48 (2010.01); H01L 33/62 (2010.01); H01L 23/498 (2006.01); H01L 33/50 (2010.01); H01L 33/52 (2010.01);
U.S. Cl.
CPC ...
H01L 33/36 (2013.01); H01L 21/28 (2013.01); H01L 33/486 (2013.01); H01L 33/62 (2013.01); H01L 23/49805 (2013.01); H01L 33/50 (2013.01); H01L 33/52 (2013.01); H01L 2924/0002 (2013.01);
Abstract

According to one embodiment, a light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a first insulating layer, a p-side interconnect layer, an n-side interconnect layer and a second insulating layer. The semiconductor layer includes a first surface, a second surface opposite to the first surface, and a light emitting layer. The p-side electrode is provided on the second surface in a region including the light emitting layer. The n-side electrode is provided on the second surface in a region not including the light emitting layer. The p-side interconnect layer includes a p-side external terminal exposed from the second insulating layer at a third surface having a plane orientation different from a plane orientation of the first surface and a plane orientation of the second surface. The n-side interconnect layer includes an n-side external terminal exposed from the second insulating layer at the third surface.


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