The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2015

Filed:

Mar. 25, 2013
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Syamsul Hani Hasran, Paya Dalam, MY;

Ian Eu Meng Chan, Ipoh, MY;

Wai Loon Ho, Ipoh, MY;

Lee Shyuan Heng, Bukit Mertajam, MY;

Min Meng Loo, Lebuh Tunku Kudin, MY;

Mohd Yusuf Abdul Hamid, Taman Desa Relau, MY;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/455 (2006.01);
U.S. Cl.
CPC ...
G06F 9/455 (2013.01); G06F 17/5022 (2013.01);
Abstract

Techniques for emulating a logic block in an integrated circuit (IC) design are provided. The techniques include identifying a plurality of logic elements that are connectable to formal logic block. These logic elements are connected to perform logic functions associated with the logic block. The logic block may be a physical logic block on one IC design and a non-existent logic block on another IC design. The logic elements and associated connections form an emulated logic block.


Find Patent Forward Citations

Hasran, Syamsul. (2015). Block emulation techniques in integrated circuits (U.S. Patent No. 8954907). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8954907

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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