The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2015

Filed:

Aug. 30, 2013
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Masatsugu Ogawa, Kanagawa-ken, JP;

Teruo Takagiwa, Kanagawa-ken, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/10 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes n (n being a natural number of 2 or more) data retention circuits connected to a data input/output terminal; n buses connected respectively to the n data retention circuits; m×n data latch circuits connected to the buses, with m (m being a natural number of 2 or more) data latch circuits being connected per one of the buses; and a selection circuit configured to simultaneously perform data transfer from/to the data retention circuits for a plurality of the data latch circuits in units of a group including the plurality of the data latch circuits, the data latch circuits being divided into the groups so that not all the data latch circuits connected to the same bus are included in the same group.


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