Semiconductor memory device

Abstract

A semiconductor memory device includes a first core region and a second core region disposed along a first reference line parallel to a major axis, the first reference line connecting an input pad and an output pad; first and second cell blocks disposed in the first core region along the first reference line; third and fourth cell blocks disposed in the second core region along the first reference line; and a repeater positioned between the third and fourth cell blocks, and configured to receive data outputted from the first cell block or the second cell block, amplify the received data and transfer the amplified data to a second global input/output line. Reducing the number of needed global input/output lines leads to layout area reduction. Moreover, since repeaters are driven in read operations for a limited number of cell blocks, signal gain may be reduced, thus reducing overall power consumption.