The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2015

Filed:

Mar. 20, 2012
Applicants:

Yasuhiro Shiino, Yokohama, JP;

Shigefumi Irieda, Yokohama, JP;

Kenri Nakai, Fujisawa, JP;

Eietsu Takahashi, Yokohama, JP;

Koki Ueno, Yokohama, JP;

Inventors:

Yasuhiro Shiino, Yokohama, JP;

Shigefumi Irieda, Yokohama, JP;

Kenri Nakai, Fujisawa, JP;

Eietsu Takahashi, Yokohama, JP;

Koki Ueno, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 11/56 (2006.01); G11C 16/06 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5628 (2013.01); G11C 16/06 (2013.01); G11C 16/0483 (2013.01); G11C 16/3418 (2013.01);
Abstract

A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates. In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.


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