The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2015

Filed:

Sep. 27, 2013
Applicant:

Panasonic Corporation, Osaka, JP;

Inventors:

Tsuyoshi Koike, Shiga, JP;

Shigeo Houmura, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/289 (2006.01); H03K 3/037 (2006.01); G01R 31/3185 (2006.01); G11C 29/12 (2006.01); G11C 29/32 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0375 (2013.01); G01R 31/318541 (2013.01); G11C 29/1201 (2013.01); G11C 29/32 (2013.01); G11C 2029/3202 (2013.01);
Abstract

A combination circuit generates first and second internal signals according to first and second input signals, respectively. A first master latch circuit selectively captures and holds a scan-in signal and the first internal signal, and generates a first output signal and a first intermediate signal based on the signals thus captured and held. A first slave latch circuit selectively captures and holds the first intermediate signal and the second internal signal, and generates a second output signal and a scan-out signal based on the signals thus captured and held. This arrangement reduces a circuit scale and power consumption of the input circuited provided in a semiconductor integrated circuit to which a scan path test method is applied.


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