The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2015

Filed:

Mar. 14, 2013
Applicants:

Junkyu Yang, Seoul, KR;

Phil Ouk Nam, Hwaseong-si, KR;

Youngseon Son, Hwaseong-si, KR;

Kwangyoung Lee, Suwon-si, KR;

Kihyun Hwang, Seongnam-si, KR;

Inventors:

Junkyu Yang, Seoul, KR;

Phil Ouk Nam, Hwaseong-si, KR;

Youngseon Son, Hwaseong-si, KR;

Kwangyoung Lee, Suwon-si, KR;

Kihyun Hwang, Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 27/11578 (2013.01); H01L 27/11556 (2013.01);
Abstract

A three-dimensional (3D) nonvolatile memory device includes a vertical stack of nonvolatile memory cells on a substrate having a region of first conductivity type therein. A dopant region of second conductivity type is provided in the substrate. This dopant region forms a P-N rectifying junction with the region of first conductivity type and has a concave upper surface that is recessed relative to an upper surface of the substrate upon which the vertical stack of nonvolatile memory cells extends. An electrically insulating electrode separating pattern is provided, which extends through the vertical stack of nonvolatile memory cells and into the recess in the dopant region of second conductivity type.


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